Regardless of size, most digital data processing systems consist of a combinational logic network and bi-stable latch elements. The combinational logic network contains hundreds or even thousands of logic gates, such as AND and OR gates, that perform the required decision-making functions. The latches surround the combinational logic and serve as memory elements to temporarily store the input data, output data and control information.
The state of the processing system is defined by the state of all of its latches. Usually, the state of the system changes at the occurrence of each clock pulse from the clocking system. The state of the system is determined by the state of the input latches, the state of the control latches, the state of the output latches and the structure of the combinational logic network at the occurrence of each clock pulse.
A data processing system may be designed with a scan technique to provide better fault isolation so that faults in the latches are independently ascertainable from faults in the associated combinational logic. In this case, the latches are modified to function like parallel-load, serial-shift registers connected end to end. This allows reconfiguring of the latches into one extensive serial shift register for test purposes.
When so configured, a select signal is used to shift the latches to a scan mode for testing from a non-scan mode. When the latches are in the scan mode, the latches are provided with a test input signal with a serial data test pattern. The last of the latches in the serial test configuration has a test output signal representative of the serial data test pattern passing through the latches in the scan mode.
A serious problem with the implementation of the scan technique is the corruption of data stored in the DRAM's of the memory modules in the memory system when the scanning mode is initiated. This is because the latches associated with control of the DRAM's are run through an arbitrary number of transitions during scan, and their outputs can corrupt the stored data in the DRAM's if the DRAM's are not isolated from these latches during scan.
Furthermore, because of the necessity to refresh the DRAM's periodically to preserve their contents, a clock must be used to control the refresh cycles. It is desirable to single step the memory controller, or run it in bursts, during scanning operations. However, if the data processing system clock is used for this purpose, it cannot be stopped, single stepped or run in bursts of cycles without interrupting the DRAM refresh cycles.
Consequently, the scanning operation cannot be conducted on a single step basis to first scan in a test pattern, single step to system clock, and then scan out the result without interrupting the DRAM refresh cycles, if the refresh cycles are timed by the system clock. This is because the memory controller is synchronized with the system clock, and it expects an uninterrupted flow of clock pulses when controlling the DRAM's. If the system clock is single stepped, this involves stopping the system clock, and the long intervals possible between clock pulses translate to large interruptions in the timing of the control signals to the DRAM's resulting in an improperly executed refresh cycle.
Similarly, it is often desirable to run a sequence of single steps, the first of which is scanned in, then a burst of clock pulses comprising the desired number of clock cycles is applied and then the result is scanned out. As in the single step case, the memory controller expects an uninterrupted flow of clock pulses, so if the burst is not long enough, then again an improperly executed refresh cycle occurs.
Because it is important that the memory controller be synchronized to the system clock during normal operation, it is not possible to simply run the memory controller on its own asynchronous clock all the time to alleviate the DRAM refresh cycle problem.
In addition to refreshing the DRAM's, it may also be desired, while single stepping or bursting the system clocks, to perform normal operations such as write and read operations to the DRAM's. Since control of these normal operations also requires an uninterrupted flow of system clock pulses, similar problems arise as described above.